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RFT2P03L
Data Sheet July 1999 File Number 4574.2
2.1A, 30V, 0.150 Ohm, P-Channel Logic Level, Power MOSFET
This product is a P-Channel power MOSFET manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. This transistor can be operated directly from integrated circuits. Formerly developmental type TA49222.
Features
* 2.1A, 30V * rDS(ON) = 0.150 * Temperature Compensating PSPICE(R) Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFT2P03L PACKAGE SOT-223 2P03L BRAND
Symbol
D
NOTE: RFT2P03L is available only in tape and reel. Use the entire part number and add the suffix T.
G
S
Packaging
SOT-223
DRAIN (FLANGE)
SOURCE DRAIN GATE
7-7-19
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFT2P03L
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified -30 -30 20V 2.1 Figure 5 Figures 6, 14, 15 1.1 0.009 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Note 2) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-10) Qg(TH) CISS COSS CRSS RJA Pad Area = 0.171 in2 (See note 2) Pad Area = 0.068 in2 (See Tech Brief 377) Pad Area = 0.026 in2 (See Tech Brief 377) VGS = 0V to -20V VGS = 0V to -10V VGS = 0V to -2V VDD = -15V, ID 2.1A, RL = 7.1 Ig(REF) = -1.0mA (Figure 13) TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = -30V, VGS = 0V VDS = -30V, VGS = 0V, TA = 150oC VGS = 20V ID = 2.1A, VGS = -10V (Figure 9) ID = 2.1A, VGS = -4.5V (Figure 9) VDD = -15V, ID 2.1A, RL = 7.1, VGS = -10V, RGS = 21 MIN -30 -1 TYP 0.120 0.300 13 18 43 24 27 14 1.3 620 240 30 MAX -3 -1 -50 100 0.150 0.360 50 100 33 17 1.6 110 128 147 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at -10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
VDS = -25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge NOTE: 2. 110oC/W measured using FR-4 board with 0.171 in2 footprint for 1000 seconds. SYMBOL VSD trr QRR ISD = -2.1A ISD = -2.1A, dISD/dt = 100A/s ISD = -2.1A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX -1.25 49 45 UNITS V ns nC
7-7-20
RFT2P03L Typical Performance Curves Unless Otherwise Specified
1.2 POWER DISSIPATION MULTIPLIER ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) -2.5 RJA = 110oC/W -2.0
-1.5
-1.0
-0.5
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
2 1 ZJA, NORMALIZED THERMAL IMPEDANCE
0.1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
PDM t1
0.01
NOTES: DUTY FACTOR: D = t1/t2 SINGLE PULSE RJA = 110oC/W 101
t2
PEAK TJ = PDM x ZJA x RJA + TA 0.001 10-5
10-4
10-3
10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s)
102
103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100 TJ = MAX RATED TA = 25oC RJA = 110oC/W 100s -10 1ms IDM, PEAK CURRENT (A)
-30
ID, DRAIN CURRENT (A)
RJA = 110oC/W TA = 25oC
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
-10
-1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.1 -1 -10
10ms
-100
VDS, DRAIN TO SOURCE VOLTAGE (V)
-1 10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
7-7-21
RFT2P03L Typical Performance Curves Unless Otherwise Specified
-6 -20 IAS, AVALANCHE CURRENT (A) -5 ID, DRAIN CURRENT (A) -4 -3 STARTING TJ = 150oC STARTING TJ = 25oC -16 VGS = -20V VGS = -10V VGS = -7V VGS = -6V
(Continued)
-12
-2
-8
VGS = -5V VGS = -4.5V
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] -1 1 10 tAV, TIME IN AVALANCHE (ms) 100
-4 PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX TA = 25oC 0 -1.5 -3.0 -4.5 -6.0 -7.5
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
-20
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
ID, DRAIN CURRENT (A)
-16
PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX VDD = 15V
1.8 -55oC 25oC 1.6 1.4 1.2 1.0 0.8 0.6 -80 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V, ID = 2.1A
-12
150oC
-8
-4
0 0 -1.5 -3.0 -4.5 -6.0 -7.5 VGS, GATE TO SOURCE VOLTAGE (V)
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A
1.2 ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
7-7-22
RFT2P03L Typical Performance Curves Unless Otherwise Specified
750 CISS 600 C, CAPACITANCE (pF) VGS = 0V, f = 0.1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
(Continued)
-10 VGS , GATE TO SOURCE VOLTAGE (V) WAVEFORMS IN DESCENDING ORDER: ID = 2.1A ID = 1A VDD = -15V
-8
-6
450 COSS 300
-4
-2
150 CRSS 0 0 -5 -10 -15 -20 -25 -30 VDS , DRAIN TO SOURCE VOLTAGE (V)
0 0 3 6 9 Qg, GATE CHARGE (nC) 12 15
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0
+
VDD VDD
0V VGS
DUT tP IAS 0.01
IAS tP BVDSS VDS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL Qg(TH) 0 VGS= -2V VGS VDD
+
VDS
-VGS Qg(-10) VDD Qg(TOT) 0 Ig(REF)
VGS= -10V
DUT Ig(REF)
VGS= -20V
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
7-7-23
RFT2P03L Test Circuits and Waveforms
(Continued)
tON td(ON) VDS RL VGS 0 tr 10%
tOFF td(OFF) tf 10%
VDD VGS RGS
+
VDS VGS 0
90%
90%
DUT
10% 50% PULSE WIDTH 90% 50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal impedance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = -----------------------------R JA
necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
200 RJA = 75.9 - 19.3 * in(AREA) 147oC/W - 0.026in2 RJA (oC/W) 150 128oC/W - 0.068in2 110oC/W - 0.171in2 100
(EQ. 1)
In using surface mount devices such as the SOT-223 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of the PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board 2. The number of copper layers and the thickness of the board 3. The use of external heat sinks 4. The use of thermal vias 5. Air flow and board orientation 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the
50 0.01
0.1 AREA, TOP COPPER AREA (in2)
1.0
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other component side copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R JA = 75.9 - 19.3 x in ( Area ) (EQ. 2)
7-7-24
RFT2P03L PSPICE Electrical Model
.SUBCKT RFT2P03L 2 1 3 ;
CA 12 8 6.5e-10 CB 15 14 6.4e-10 CIN 6 8 5.77e-10
10
REV July 1998
ESG 8 6 + 5
LDRAIN DRAIN 2 RLDRAIN
DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -41.2 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.27e-9 LSOURCE 3 7 4.2e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 24e-3 RGATE 9 20 5.2 RLDRAIN 2 5 10 RLGATE 1 9 12.7 RLSOURCE 3 7 4.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 68e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 13 8 S1B 13 CA EGS + 6 8 GATE 1 LGATE RGATE 9 RLGATE 20
RSLC2
RSLC1 51 + 5 ESLC 51 50 RDRAIN 16
EBREAK
+ 17 18 DBODY 11
DPLCAP EVTHRES + 19 8 6
EVTEMP 18 + 22
21 MMED MSTRO
MWEAK
DBREAK LSOURCE
CIN
8
RSOURCE 7
SOURCE 3 RLSOURCE
S2A 15 14 13 S2B CB + EDS 5 8 8 14
RBREAK 17 18 RVTEMP IT 19 VBAT + 22 RVTHRES
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))} .MODEL DBODYMOD D (IS = 2e-13 RS = 3.5e-2 IKF = 0.7 XTI = 8.2 TRS1 = 6e-4 TRS2 = 5e-7 CJO = 7.3e-10 TT = 3.51e-8 M = 0.4 .MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 1e-4 TRS2 = 1e-5) .MODEL DPLCAPMOD D (CJO = 2.65e-10 IS = 1e-30 N = 10 M = 0.63) .MODEL MMEDMOD PMOS (VTO = -2.6 KP = 1.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.2) .MODEL MSTROMOD PMOS (VTO = -3.27 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD PMOS (VTO = -2.11 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 52 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.2e-4 TC2 = -1e-7) .MODEL RDRAINMOD RES (TC1 = 1.8e-2 TC2 = 2.1e-5) .MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 1.3e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = 8.8e-4 TC2 = 6.1e-6) .MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 5.7 VOFF= 2.7) VON = 2.7 VOFF= 5.7) VON = -0.1 VOFF= -2.4) VON = -2.4 VOFF= -0.1)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7-7-25
RFT2P03L SPICE Thermal Model
REV July 98 RFT2P03L CTHERM1 9 8 1.9e-5 CTHERM2 8 7 3.0e-4 CTHERM3 7 6 1.2e-3 CTHERM4 6 5 3.5e-3 CTHERM5 5 4 2.0e-2 CTHERM6 4 3 6.5e-2 CTHERM7 3 2 2.0e-1 CTHERM8 2 1 1 RTHERM1 9 8 3.5e-2 RTHERM2 8 7 8.5e-2 RTHERM3 7 6 3.5e-1 RTHERM4 6 5 1.85 RTHERM5 5 4 2.75 RTHERM6 4 3 15 RTHERM7 3 2 30 RTHERM8 2 1 50
9 JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
6
RTHERM4
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
1
AMBIENT
7-7-26
RFT2P03L
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
7-7-27

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